1. Field of the Invention
The present invention relates to the memory reconfiguration in data processing systems; and more particularly to reconfiguration of cache memory to take failing segments of the cache offline in response to the detection of hard errors in the failing segment.
2. Description of Related Art
In order to achieve high availability in data processing systems, it is desirable to be able to reconfigure failing parts of the system out of operation, and thereby continue to function in a slightly degraded mode until repairs can be accomplished. The intrinsically higher failure rate of RAMs makes this especially desirable for cache memory systems of a CPU in a large scale data processing system, such as those operating in accordance with the IBM ESA/390 architecture.
When a failing portion of a cache memory is to be reconfigured offline, it is necessary to recover the remaining good data and validate the damaged data. In the prior art, this has been accomplished in several ways. One method is to release the entire contents of the cache via whatever means is provided in the machine for this purpose. For example, in the Amdahl 580, the service processor was able to send a bus message which caused the cache control hardware to perform this function with clocks on but with the system in a quiescent state. Another similar method to accomplish the same result, but with clocks off, is to scan out the contents of the cache, search throughout the system for any other data in transit, emulate the hardware's error correction process for any damaged data, and then scan the data back into appropriate locations in main store.
It is desirable to accomplish reconfiguration of cache memory in a data processing system without suffering a quiescent state or an extended clocks off period, such as imposed by prior art reconfiguration techniques.